A digital sampled data treble control circuit has been described by Yoshimutsu Hirata in Wireless World, September 1982, pp. 77-79. This treble control circuit includes the cascade connection of a variable finite impulse response filter, a multiplier, a variable infinite impulse response filter and a second multiplier. Each of the two filters includes an additional multiplier element, thus, the cascade connection of filters and multipliers in the treble control includes a total of four multipliers.
Digital multipliers tend to be relatively complex and expensive circuit elements. Analog multipliers tend to be temperature and power supply sensitive and, thus, and require significant compensation circuitry to ensure stability. Thus, for either digital or analog sampled data treble control circuitry it is desirable to minimize the number of required multipliers.